Successive approximation register converter
US9520891B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2015 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Nov 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a successive approximation register analog-to-digital converter (SAR ADC) for providing a digital approximation of a sampled differential input signal as a result of a successive approximation operation. The SAR ADC comprises a first comparison stage configured to perform a first set of decision steps of the successive approximation operation and a second comparison stage configured to perform a second set of decision steps of the successive approximation operation. Furthermore, the SAR ADC comprises a regulation circuit configured to adjust the common mode of the input signal towards a target common mode before the second comparison stage performs the second set of decision steps. The present invention further relates to a corresponding method and a corresponding design structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.