Architecture for ensuring monotonicity in a digital-to-analog converter
US9520893B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2016 |
| Grant date | Dec 13, 2016 |
| Priority date | — |
| Expiry date | Mar 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2j current sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j−1 of the 2j current sources to the output node. One of the 2j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.