Load balancing in a system with multi-graphics processors and multi-display systems
US9524138B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Sep 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In typical embodiments a three GPU configuration is provided comprising three discrete video cards, each connected to a standard monitor placed horizontally for a 3× horizontal resolution. In this configuration, depending on the load on each GPU, the vertical split lines are dynamically adjusted. To adjust the load balancing according to these virtual split lines, the rendering clip rectangle of each GPU is adjusted, in order to reduce the number of pixels rendered by the heavily loaded GPU. These split lines define the boundary of the scene to be rendered by each GPU, and, according to some embodiments, may be moved horizontally. Thus for example if a GPU has a more complex rendering clip polygon to render than the other GPUs, the neighboring GPUs may render the rendering clip polygon it displays plus a portion of the rendering clip polygon to be displayed by heavily loaded GPU. The assisting GPUs transmit to the heavily loaded GPU the portion of the rendering clip polygon to be displayed by GPU via the chipset with a peer-to-peer protocol or through a communication bus. The split line is dynamically adjusted after each scene.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.