Flash memory cells wear reduction
US9524790B1 · kind B1 · utility
13Cited by
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31Claims
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Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for wear reduction of a flash memory module, the method may include reading data stored in a group of flash memory cells to provide a read data; wherein the reading comprise supplying a bias voltage that is lower than a write bias voltage; wherein the write bias voltage was supplied to the group of flash memory cells during a writing of the data to the group of flash memory cells; and decoding the read data, by applying a decoding process of a given complexity, to provide decoded data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.