Methods for forming CMOS inverters
US9524912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2016 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | May 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.