Patent · US Active

Variable gate width FinFET

US9525068B1 · kind B1 · utility

6Cited by

1References

9Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Mayank Gupta · Sunnyvale, US
Peter Smeys · White Plains, US

Key dates

Filing date	Mar 15, 2013
Grant date	Dec 20, 2016
Priority date	—
Expiry date	Mar 15, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/038
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An improved FinFET has a gate structure on only a portion of the available surface on a fin, thereby providing a FinFET with a finer granularity width dimension. To form the FinFET, a first etch-resistant sacrificial layer and a second etch-resistant spacer layer are formed on the fin. The spacer layer is etched anisotropically to remove the spacer layer from the top and upper sidewalls of the fin while leaving the spacer layer on the lower sidewalls of the FinFET. A gate dielectric and conducting layer are then deposited and shaped to form a structure that is effective as a gate only on the top and upper sidewalls of the fin.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.