Patent · US Active

Low clocking power flip-flop

US9525401B2 · kind B2 · utility

0Cited by

18References

20Claims

0Family size

Assignee

NVIDIA Corporation · US

Inventors

Xi Zhang · Ottawa, CA
Hwong-Kwo Lin · Palo Alto, US
Ge Yang · Beijing, CN
Lingfei Deng · Santa Clara, US

Key dates

Filing date	Mar 11, 2015
Grant date	Dec 20, 2016
Priority date	—
Expiry date	Mar 11, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/21
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.