High speed, low power, isolated multiplexer
US9525408B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2013 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Oct 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses are disclosed for a high speed, low power, isolated multiplexer having architecture and operation that control current flow to minimize coupling and power consumption. Multiplexer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit, a multiplexer disabling circuit operated to disable a multiplexer when input circuits are disabled by the selection circuit, a buffer having a buffer input disabling circuit operated to additionally disable a buffer input circuit when it is also disabled by a buffer selection circuit and a buffer disabling circuit operated to disable a buffer when the buffer input circuit is disabled by the buffer selection circuit. Any one or more of these features may be implemented to improve isolation performance. The architecture may be operated by a one-hot coding scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.