Referenceless clock recovery circuit with wide frequency acquisition range
US9525544B2 · kind B2 · utility
1Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2015 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Jun 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A full-rate referenceless clock-data recovery architecture with neither a frequency detector nor a lock detector that allows both frequency and phase locking in a single loop. According to one embodiment, a referenceless clock data recovery (CDR) circuit, comprises a digital control circuit (DCC), a phase and strobe point detector circuit (PSPD), and an LC voltage control oscillator (LC VCO) electrically coupled to the PSPD and DCC such that a frequency of the LC VCO decreases when a negative strobe point is detected and an initial frequency of the LC VCO is higher than an input data bit rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.