Phase locked loop for preventing harmonic lock, method of operating the same, and devices including the same
US9525545B2 · kind B2 · utility
1Cited by
6References
8Claims
0Family size
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Key dates
| Filing date | Feb 17, 2014 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Aug 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.