Image processing circuit and image processing method for generating interpolated image
US9525873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2013 |
| Grant date | Dec 20, 2016 |
| Priority date | — |
| Expiry date | Jul 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/587
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image processing circuit and an image processing method are provided. The image processing circuit comprises a full search engine and a frame rate conversion (FRC) engine. The full search engine executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to the reference image and the current image. The FRC engine analyzes a scene characteristic from the current image according to SAD distribution. The FRC engine adjusts at least one of the control parameters according to the scene characteristic. The FRC engine generates an interpolated image according to the reference image, the current image and the control parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.