Rasterization of compute shaders
US9529575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jun 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/456
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are compiler algorithms that partition a compute shader program into maximal-size regions, called thread-loops. The algorithms may remove original barrier-based synchronization yet the thus-transformed shader program remains semantically equivalent to the original shader program (i.e., the transformed shader program is correct). Moreover, the transformed shader program is amenable to optimization via existing compiler technology, and can be executed efficiently by CPU thread(s). A Dispatch call can be load-balanced on a CPU by assigning single or multiple CPU threads to execute thread blocks. In addition, the number of concurrently executing thread blocks do not overload the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.