Multithread processor with different schedule pattern cycle state for handling interrupt processing
US9529597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2013 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Oct 10, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that continuously outputs a thread selection signal uniformly in a first period of a cycle of the first schedule pattern in accordance with a first schedule pattern or continuously outputs the thread selection signal uniformly in a second period of a cycle of the second schedule pattern in accordance with a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads, and an execution pipeline that executes an instruction output from the first selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.