Double consecutive error correction
US9529665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jan 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/616
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Double consecutive error correction is described. An integrated circuit with double consecutive error correction logic includes a data storage structure operative to store a set of data and a first error correction code that corresponds to the set of data. The set of data includes multiple data bits. The first error correction code was generated using a generator matrix having multiple bit groups, each bit group including a unique set of bit positions. The integrated circuit also includes an error correction code generator operative to generate, using the generator matrix, a second error correction code that corresponds to the set of data. The integrated circuit further includes a comparator operative to generate a comparison result of the first error correction code and the second error correction code. The integrated circuit includes a data corrector operative to correct two consecutive data bits of the set of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.