Method and system for using NAND page buffers to improve the transfer buffer utilization of a solid state drive
US9529668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Nov 6, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.