Interpolation circuitry and techniques for graphics processing
US9530237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Apr 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to interpolation for texture mapping. In some embodiments, a graphics unit includes circuitry configured to map a texture to a screen space such that a set of multiple in the screen space falls between first and second adjacent texels of the texture in a first dimension. In some embodiments, the graphics unit also includes texture processing circuitry configured to perform different types of interpolation for pixels in the group of pixels. In these embodiments, this includes determining pixel attributes for first and second end groups of pixels in the set of pixels using a nearest-neighbor interpolation technique and attributes of the first and second texels respectively. In these embodiments, this also includes determining pixel attributes for an intermediate group of pixels in the set of pixels using a second, different interpolation technique and attributes of both the first and second texels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.