Gate drive on array unit and method for driving the same, gate drive on array circuit and display apparatus
US9530345B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 10, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Apr 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided are a GOA unit and driving method, a GOA circuit and a display apparatus. A first node control unit (31) pulls a first node (PU) to a voltage at a first level terminal (CN) under the control of a first input terminal (IN), or to a voltage at a second level terminal (CNB) under the control of a second input terminal (INPUT). A second node control unit (32) pulls a second node (PD) to a voltage at a third level terminal (VGH) under the control of the first level terminal (CN), the second level terminal (CNB), a second clock signal terminal (CK2) and a third clock signal terminal (CK3), or to a voltage at a fourth level terminal (VGL) under the control of the first node (PU). An output unit (33) outputs a signal at the first clock signal terminal (CK1) under the control of the first node (PU), or pulls the output terminal (OUTPUT) to the voltage at the fourth level terminal (VGL) under the control of the second node (PD).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.