Method of writing memory with regulated ground nodes
US9530487B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Dec 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.