Display circuitry with improved transmittance and reduced coupling capacitance
US9530801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jun 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2202/42
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. A first low-k dielectric layer may be formed on the passivation layer. Data line routing structures may be formed on the first low-k dielectric layer. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. The first and second low-k dielectric layers may be formed from material having substantially similar refractive indices to maximize backlight transmittance and may have appropriate thicknesses so as to minimize parasitic capacitive loading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.