Patent · US Active

False-trigger free power-rail ESD clamp protection circuit

US9531188B2 · kind B2 · utility

1Cited by

2References

11Claims

0Family size

Assignee

Peking University · CN

Inventors

Yuan Wang · Beijing, CN
Guangyi Lu · Beijing, CN
Jian Cao · Wilmette, US
Xing Zhang · Beijing, CN

Key dates

Filing date	Nov 20, 2013
Grant date	Dec 27, 2016
Priority date	—
Expiry date	Nov 20, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH02H9/046
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

A false-trigger free power-rail ESD clamp protection circuit includes an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel. The circuit, in a smaller layout area, has very strong electrostatic charge discharge capability under ESD impact, little power leakage during normal power-up, and relatively strong false-trigger immunity capability for quick power-up.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.