Method and circuitry for CMOS transconductor linearization
US9531335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Aug 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/30111
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor. A low impedance bypass circuit re-circulates second order distortion current that is induced by second-order distortion in drain currents of the first P-channel transistor and the first N-channel transistor, through the first N-channel transistor and first P-channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.