Integrated circuit with low phase noise clock distribution network
US9531356B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Nov 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/13
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a clock distribution circuit and a logic block circuit. The clock distribution circuit is segregated from the logic block circuit to restrict contributors to phase noise to the clock distribution section of the circuit. The clock distribution circuit includes a front-end amplifier which buffers a clock input signal to a differential clock signal. The front-end amplifier is configured with as few components as possible and the components are selected for high current density and sized to minimize contributions to phase noise in the clock distribution circuit. The clock distribution circuit further includes an output latch circuit that receives the output signal of the logic block circuit and the low phase noise differential clock input signal from the front-end amplifier circuit. The output latch circuit re-clocks the final output of the integrated circuit. The output is representative of the output values determined by the logic block circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.