Limiting aging effects in analog differential circuits
US9531398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2016 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Feb 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2872
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.