System and method for saddle point locking detection during clock and data recovery
US9531529B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method and apparatus for detecting clock and data recovery loop saddle-point locking in an electronic circuit. Embodiments may include receiving a signal at a primary clock and data recovery (“CDR”) loop associated with the electronic circuit and processing the signal using at least one of a first order CDR loop and a second order CDR loop included within the primary CDR loop. Embodiments may further include determining whether a fast-phase lock module is required, wherein determining includes determining two transitions in a sampling triplet. If it is determined that the fast-phase lock module is required, embodiments may include providing a trigger signal to the fast-phase lock module. Embodiments may further include receiving the trigger signal at the fast-phase lock module associated with the electronic circuit and performing a fast-phase lock operation on the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.