Methods and devices for fixed execution flow multiplier recoding and scalar multiplication
US9531531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2015 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | May 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/3066
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
One feature pertains to an electronic device that includes a memory circuit and a processing circuit. The processing circuit computes a scalar multiplication output Z where Z=k·P by receiving an input multiplier k and a base P, and adds a modifier s to the input multiplier k to generate k′. The processing circuit also computes an intermediate scalar multiplication output Z′ where Z′=k′·P by using a digit expansion of k′ that includes a sequence of digits ki belonging to a digit set D. Additionally, the processing circuit subtracts s·P from Z′ to obtain the scalar multiplication output Z if k′ is odd or subtracts (s+1)·P from Z′ to obtain the scalar multiplication output Z if k′ is even. The scalar multiplier output Z may be used in a cryptographic security algorithm to secure data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.