Channel coding optimized for low-latency data
US9531843B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jul 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0078
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An encoding system encodes 8-bit data and control characters into 10-bit symbols. The 10-bit symbols have odd parity such that a single bit error results in an illegal code. Each 8-bit character maps either to a 10-bit symbol with balanced disparity or a pair of 10-bit symbols that collectively have balanced disparity. By periodically inserting an idle character that includes a run of seven consecutive like bits, a 1 MHz pilot tone is embedded in the data stream. The boundary of 10-bit symbols can be identified by locating a run of seven consecutive characters. 10-bit control symbols corresponding to 8-bit control characters are transmitted without reducing the bandwidth available for data transmission by replacing some or all of the preamble or idle portions of an Ethernet packet with the 10-bit control symbols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.