Efficient use of branch delay slots and branch prediction in pipelined computer architectures
US9535701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2014 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jan 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined processor selects an instruction fetch mode from a number of fetch modes including an executed branch fetch mode, a predicted fetch mode, and a sequential fetch mode. Each branch instruction is associated with branch delay slots, the size of which can be greater than or equal to zero, and can vary from one branch instance to another. Branch prediction is used to fetch instructions, with the source of information for predictions deriving from a last instruction in the branch delay slots. When a prediction error occurs, the executed branch fetch mode uses an address from branch instruction evaluation to fetch a next instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.