Automatic communication and optimization of multi-dimensional arrays for many-core coprocessor using static compiler analysis
US9535826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2014 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jul 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.