Using a decrementer interrupt to start long-running hardware operations before the end of a shared processor dispatch cycle
US9535846B2 · kind B2 · utility
1Cited by
5References
13Claims
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Key dates
| Filing date | Jul 28, 2014 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Nov 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and computer program products to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.