Processing system with interspersed processors and communication elements having improved communication routing
US9535877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2014 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jan 20, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes processors and dynamically configurable communication elements (DCCs) coupled together in an interspersed arrangement. A source device may transfer a data item through an intermediate subset of the DCCs to a destination device. The source and destination devices may each correspond to different processors, DCCs, or input/output devices, or mixed combinations of these. In response to detecting a stall after the source device begins transfer of the data item to the destination device and prior to receipt of all of the data item at the destination device, a stalling device is operable to propagate stalling information through one or more of the intermediate subset towards the source device. In response to receiving the stalling information, at least one of the intermediate subset is operable to buffer all or part of the data item.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.