In-hierarchy circuit analysis and modification
US9536036B1 · kind B1 · utility
2Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Jun 24, 2014 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jun 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performing RC analysis in a hierarchical circuit design includes: accessing hierarchical circuit data in the hierarchical circuit design, the hierarchical circuit data comprising top-level data and lower-level block data; obtaining hierarchical RC information; combining RC information on boundary paths between blocks and RC information on boundary paths within blocks to generate boundary RC information; performing RC analysis using the boundary RC information to determine a timing delay; and comparing the timing delay with a desired delay to determine whether an RC timing is closed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.