Semiconductor device having a plurality of electric field relaxation layers and method for manufacturing same
US9536942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2012 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Oct 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.