Semiconductor devices including contact patterns having a rising portion and a recessed portion
US9536968B2 · kind B2 · utility
6Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2015 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | May 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices may include a gate pattern and a contact pattern disposed on an active region. The contact pattern may include a recessed portion near the gate pattern, and a rising portion away from the gate pattern. The gate pattern may include a gate insulating layer and a gate electrode disposed on the gate insulating layer. An upper surface of the recessed portion may be lower than an upper surface of the rising portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.