Methods of manufacturing semiconductor devices including gate patterns with sidewall spacers and capping patterns on the sidewall spacers
US9536983B2 · kind B2 · utility
3Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/511
Abstract
A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.