Multilevel inverters and their components
US9537425B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2014 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jul 1, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilevel inverter includes a first half bridge in series with a second half bridge, each comprising a switch having a channel. The switch is configured to block a substantial voltage in a first direction during a first mode of operation, to conduct substantial current through the channel in the first direction during a second mode of operation, and to conduct substantial current through the channel in a second direction during a third mode of operation. During the third mode of operation, a gate of the switch is biased relative to a source of the switch at a voltage that is less than a threshold voltage of the switch. The inverter may also include a third half bridge. The inverter can be configured such that in operation, switches of the third half bridge are switched at a substantially lower frequency than the switches of the first and second half bridges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.