Sampled analog loop filter for phase locked loops
US9537492B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2015 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jun 19, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.