Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same
US9537511B2 · kind B2 · utility
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3References
16Claims
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Key dates
| Filing date | Nov 6, 2013 |
| Grant date | Jan 3, 2017 |
| Priority date | — |
| Expiry date | Jul 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.