Fused multiply add operations using bit masks
US9542154B2 · kind B2 · utility
10Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2013 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | May 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/764
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.