Memory address collision detection of ordered parallel threads with bloom filters
US9542193B2 · kind B2 · utility
2Cited by
15References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Aug 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.