Error detection on a low pin count bus
US9542251B2 · kind B2 · utility
0Cited by
18References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2013 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Mar 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods that implement communication of error information on a bus, including a bus having a small number of pins are disclosed. In one embodiment, an apparatus includes an interface circuit configured to couple to a bus and one or more sideband signals. The sideband signals may be used to communicate error information such as parity information for a bus that does not otherwise have this capability. In some embodiments, parity information may be driven on the bus during a portion of a bus transaction corresponding to unused address bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.