Interrupt suppression strategy
US9542345B2 · kind B2 · utility
2Cited by
23References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2012 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed embodiments provide a system that suppresses interrupts to facilitate efficient use of a processor in a computer system. The system includes a node that transmits a first interrupt to the processor upon receiving a first packet for processing at the processor and disables subsequent interrupts to the processor during an interrupt-suppression state in the processor. The system also includes the processor, which processes the first packet upon receiving the first interrupt and transmits a first acknowledgment of the first packet to the node to enable the interrupt-suppression state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.