Method and design apparatus
US9542519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Nov 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer sets a first timing condition for plural registers included in first design information of a semiconductor integrated circuit, and executes first logic synthesis to generate second design information. The computer sets, for the registers, a second timing condition having a smaller timing margin than the first timing condition, and executes second logic synthesis to generate third design information. The computer calculates an area change rate caused by a difference between the timing conditions, on the basis of the second and third design information with respect to each logic cone including a register at its end point, and categorizes the registers into a first group and a second group having smaller change rates than the first group, according to the change rate. The computer executes third logic synthesis with the second timing condition set for the first group and the first timing condition set for the second group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.