Efficient hardware implementation of spiking networks
US9542643B2 · kind B2 · utility
25Cited by
6References
44Claims
0Family size
Assignee
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Key dates
| Filing date | May 1, 2014 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Mar 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.