Semiconductor device and electronic device
US9542977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Apr 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.