SRAM core cell design with write assist
US9542992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2013 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Sep 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.