Memory array and coupled TCAM architecture for improved access time during search operation
US9543015B1 · kind B1 · utility
13Cited by
1References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first ternary content addressable memory (TCAM), a second TCAM, a memory array coupled to the first and second TCAMs, a first priority logic coupled between the first TCAM and the memory array, a second priority logic coupled between the second TCAM and the memory array, and a look-ahead signal generated by the first priority logic and provided to the second priority logic. Match lines from the first and second TCAMs are coupled to respective word lines in the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.