Semiconductor memory device, control method, and memory system
US9543033B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2016 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Mar 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a memory cell array, a first circuit, and a second circuit. The first circuit executes program and read. The program is processing for changing a threshold voltage of a memory cell to a voltage according to data. The data includes first data of a bit and second data of a bit. The program of the second data is executed after the program of the first data. The read includes measuring the threshold voltage. The second circuit manipulates a flag in accordance with execution of the program of the second data. In a case where the second data is a target of the read, the second circuit refers to the flag. In a case where the flag indicates non-execution of the program of the second data, the second circuit aborts the measuring before the measuring of the threshold voltage is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.