Interconnect array pattern with a 3:1 signal-to-ground ratio
US9543241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2014 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Dec 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/6627
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.