Semiconductor device
US9543315B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2016 |
| Grant date | Jan 10, 2017 |
| Priority date | — |
| Expiry date | Jul 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
The memory cell includes a gate insulating film, a control gate electrode, a cap insulating film, a cap layer, another gate insulating film, and a memory gate electrode. A laminated capacitive element includes a capacitive electrode which is constituted by a sub-electrode and another sub-electrode formed of mesa portions (protruding portions) disposed on the sub-electrode at a predetermined interval and each having an upper surface and side surfaces, a capacitive insulating film which is formed along an upper surface of the sub-electrode and the upper surface and the side surfaces of the another sub-electrode, and another capacitive electrode which is formed on the capacitive insulating film. Further, the control gate electrode and the sub-electrode are made of a conductor film, the cap layer and the another sub-electrode are made of other conductor film, and the memory gate electrode and the another capacitive electrode are made of another conductor film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.