Patent · US Active

High voltage LDMOS device with an increased voltage at source (high side) and a fabricating method thereof

US9543432B2 · kind B2 · utility

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8References

9Claims

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Assignee

Shanghai Huahong Grace Semiconductor Manufacturing Corporation · CN

Inventors

Wei Yue · Nanhu, CN
Junjun XING · Shanghai, CN
Wenqing Yang · Nanhu, CN

Key dates

Filing date	Dec 29, 2015
Grant date	Jan 10, 2017
Priority date	—
Expiry date	Dec 29, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/393
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A high voltage LDMOS device having high side source voltage, an n type buried layer and a p type buried layer situated on the interface between a p type substrate and an n type epitaxial layer; a lateral surface of the n type buried layer and a lateral surface of the p type buried layer not in contact, and are distant from one another with a distance, thereby increasing the withstand voltage between the n type buried layer and the p type buried layer; the p type buried layer and the drain overlap at least partially in a vertical direction, enabling the p type buried layer to exert a reduced surface field action on the drain, to increase the withstand voltage of the drain against the source; the source and the body terminal centrally on top of the n type buried layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.